SPAR: a schematic place and route system - Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on

This paper presents an approach to the automatic Functional identiJication occurs when the designer sees generation of schematic diagrams from circuit descriptions. The functionally interconnected modules located in proximity heuristics which make up the system are based on two princito each other with separation between distinct groups of ples of schematics readability: Functional Zdenfification and Traceability. SPAR’S generation process is broken into five disTwo common Of struttinct phases: partitioning the netlist, placement of components tures would be a single gate enabling several others as a on the page, global routing, local routing, and the addition of fan-out stmcture, and two cross-coupled gates as a flipI/O modules.-All phases of the generation process use a two dimensional space management technique based on virtual tile spaces. The global router is guided by a cost function consisting of both congestion and wirelength estimates. The local router uses a constraint-propagation technique to optimize the traceability of lines through congested areas. The data structures and algorithms used allow the system to support incremental additions to the schematic without complete regeneration. We describe a technique for evaluating the quality of schematic drawings, and apply this to our results.